The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2025

Filed:

Sep. 12, 2022
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Hajime Kimura, Kanagawa, JP;

Takahiro Fukutome, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G11C 11/404 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/12 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/32 (2006.01); G11C 16/34 (2006.01); H10D 1/68 (2025.01); H10D 30/67 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10D 87/00 (2025.01); H10D 99/00 (2025.01); G11C 16/06 (2006.01); G11C 16/28 (2006.01); H01L 21/02 (2006.01); H01L 21/027 (2006.01); H01L 21/443 (2006.01); H01L 21/4763 (2006.01); H10B 41/27 (2023.01); H10D 30/62 (2025.01); H10D 88/00 (2025.01);
U.S. Cl.
CPC ...
G11C 11/40 (2013.01); G11C 11/404 (2013.01); G11C 16/3418 (2013.01); H10D 1/692 (2025.01); H10D 30/6755 (2025.01); H10D 86/423 (2025.01); H10D 86/60 (2025.01); H10D 87/00 (2025.01); H10D 99/00 (2025.01); G11C 16/0483 (2013.01); G11C 16/06 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/12 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/28 (2013.01); G11C 16/32 (2013.01); H01L 21/02164 (2013.01); H01L 21/02178 (2013.01); H01L 21/02181 (2013.01); H01L 21/02205 (2013.01); H01L 21/02211 (2013.01); H01L 21/0228 (2013.01); H01L 21/02565 (2013.01); H01L 21/0262 (2013.01); H01L 21/0273 (2013.01); H01L 21/443 (2013.01); H01L 21/47635 (2013.01); H10B 41/27 (2023.02); H10D 30/6211 (2025.01); H10D 88/00 (2025.01);
Abstract

An object is to shorten the time for rewriting data in memory cells. A memory module includes a first memory cell, a second memory cell, a selection transistor, and a wiring WBL. The first memory cell includes a first memory node. The second memory cell includes a second memory node. One end of the first memory cell is electrically connected to the wiring WBLthrough the selection transistor. The other end of the first memory cell is electrically connected to one end of the second memory cell. The other end of the second memory cell is electrically connected to the wiring WBL. When the selection transistor is on, data in the first memory node is rewritten by a signal supplied through the selection transistor to the wiring WBL. When the selection transistor is off, data in the first memory node is rewritten by a signal supplied through the second memory node to the wiring WBL


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