The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 16, 2025
Filed:
Jan. 30, 2024
Applicant:
Arm Limited, Cambridge, GB;
Inventors:
Andy Wangkun Chen, Austin, TX (US);
Yew Keong Chong, Austin, TX (US);
Assignee:
Arm Limited, Cambridge, GB;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 5/14 (2006.01); G11C 11/417 (2006.01);
U.S. Cl.
CPC ...
G11C 5/148 (2013.01); G11C 7/1003 (2013.01); G11C 11/417 (2013.01);
Abstract
Inrush current in a memory such as SRAM cache may be managed by using one or more integrated delay elements such as inverters, RC delay lines, and the like to significantly slow down power down signal propagation between memory instances in a memory array. The delay in some examples may be between memory instances, while in other examples the delay is also introduced between bitcell arrays within a memory instance. By staggering the power up times of interconnected or chained memory instances, inrush current when powering the memory instances on or resuming from an inactive state may be reduced.