The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2025

Filed:

Aug. 06, 2024
Applicant:

Lx Semicon Co., Ltd., Daejeon, KR;

Inventors:

Tai Ming Piao, Daejeon, KR;

Won Kim, Daejeon, KR;

Jin Woo Kim, Daejeon, KR;

Assignee:

LX SEMICON CO., LTD., Daejeon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3688 (2013.01); G09G 2310/027 (2013.01); G09G 2310/0291 (2013.01); G09G 2320/0276 (2013.01);
Abstract

A buffer can include a first output adjustment unit configured to output a first signal, and a second output adjustment unit configured to output a second signal. The first output adjustment unit can include a first input stage configured to adjust a control current according to a difference between a first input voltage and a first output voltage, and a first output stage configured to output the first output voltage as the first signal. The first output voltage can be a voltage between a first level voltage and a second level voltage. The first input stage can be connected to a third power line that supplied a third level voltage. The first level voltage can be greater than the second level voltage. The second level voltage can be greater than the third level voltage.


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