The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2025

Filed:

Jun. 23, 2023
Applicant:

Sage Electrochromics, Inc., Faribault, MN (US);

Inventors:

Yan Wang, Lakeville, MN (US);

Frank Mcgrogan, Faribault, MN (US);

Bolei Di, Woodbury, MN (US);

Yigang Wang, Maple Grove, MN (US);

Assignee:

SAGE Electrochromics, Inc., Faribault, MN (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01N 27/04 (2006.01); C23C 14/34 (2006.01); E06B 9/24 (2006.01); G02F 1/1343 (2006.01); G02F 1/155 (2006.01); H01J 37/34 (2006.01);
U.S. Cl.
CPC ...
G01N 27/041 (2013.01); C23C 14/34 (2013.01); E06B 9/24 (2013.01); G02F 1/13439 (2013.01); G02F 1/155 (2013.01); E06B 2009/2464 (2013.01); H01J 37/3405 (2013.01);
Abstract

A method implemented by a system for manufacturing a device having a coated transparent substrate is provided. The method includes providing the device having a transparent substrate. The method also includes coating the transparent substrate with a first transparent conductive oxide (TCO) layer in accordance with one or more parameters. The coating the transparent substrate comprises performing a physical deposition process on the transparent substrate. The method further includes determining a resistance across the first TCO layer. In addition, the method includes determining whether the resistance across the first TCO layer is within a resistance range. The method also includes in response to determining that the resistance across the first TCO layer is within the resistance range, coating the device with a second TCO layer in accordance with the one or more parameters to provide a resistance across the second TCO layer that is within the resistance range.


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