The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2025

Filed:

Feb. 12, 2024
Applicant:

Maxeon Solar Pte. Ltd., Singapore, SG;

Inventors:

Kieran Mark Tracy, San Jose, CA (US);

David D. Smith, Campbell, CA (US);

Venkatasubramani Balu, Santa Clara, CA (US);

Asnat Masad, Mountain View, CA (US);

Ann Waldhauer, La Honda, CA (US);

Assignee:

Maxeon Solar Pte. Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10F 77/20 (2025.01); H10F 10/14 (2025.01); H10F 10/165 (2025.01); H10F 10/166 (2025.01); H10F 71/00 (2025.01); H10F 71/10 (2025.01); H10F 77/14 (2025.01); H10F 77/70 (2025.01);
U.S. Cl.
CPC ...
H10F 77/219 (2025.01); H10F 10/146 (2025.01); H10F 77/223 (2025.01); H10F 77/227 (2025.01); H10F 10/165 (2025.01); H10F 10/166 (2025.01); H10F 71/103 (2025.01); H10F 71/121 (2025.01); H10F 77/147 (2025.01); H10F 77/211 (2025.01); H10F 77/703 (2025.01);
Abstract

Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.


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