The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2025

Filed:

Jan. 17, 2023
Applicant:

Fast Sic Semiconductor Incorporated, Hsinchu, TW;

Inventors:

Cheng-Tyng Yen, Hsinchu, TW;

Hsiang-Ting Hung, Hsinchu, TW;

Fu-Jen Hsu, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H10D 30/66 (2025.01); H10D 62/10 (2025.01); H10D 62/17 (2025.01); H10D 62/832 (2025.01);
U.S. Cl.
CPC ...
H10D 30/66 (2025.01); H10D 62/109 (2025.01); H10D 62/393 (2025.01); H10D 62/8325 (2025.01);
Abstract

A silicon carbide semiconductor device comprises a drift layer, a plurality of transistor cells and a gate structure. Each of the transistor cells comprises a first doped region, a second doped region, a third doped region and a fourth doped region. The first doped region is disposed in the drift layer. The second doped region is disposed in the first doped region. The third doped region is disposed in the first doped region and adjacent to the second doped region. The fourth doped region is disposed in or on the first doped region to form a channel region and is configured in a way such that the channel region is not fully depleted when a driving gate voltage applied to the semiconductor device is zero and the channel region is fully depleted when the driving gate voltage is less than a negative threshold voltage.


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