3d synapse device stack, 3d stackable synapse array using the 3d synapse device stacks and method of fabricating the stack

Abstract

Provided is a 3D synapse device stack, a 3D stackable synapse array using the same, and a method for manufacturing the 3D synapse device stack. The 3D synapse device stack comprises: a body electrode disposed on a substrate in a vertical direction; a plurality of first insulating layers and third oxide layers alternately stacked on the outer circumferential surface of the body electrode; a plurality of semiconductor bodies disposed on an outer circumferential surface of the third oxide layer; a plurality of sources alternately stacked with first insulating layers on outer circumferential surfaces of the semiconductor bodies positioned on a first side surface of the body electrode; a plurality of drains alternately stacked with first insulating layers on outer circumferential surfaces of the semiconductor bodies positioned on a second side surface of the body electrode; a plurality of word lines alternately stacked with first insulating layers on outer circumferential surfaces of the semiconductor bodies positioned on a third side surface of the body electrode; and an insulator stack positioned between the word line and the semiconductor body. The semiconductor body, the source, the drain, the insulator stack and the word line located on the same layer on the outer peripheral surface of the body electrode constitute a synapse device, or a part thereof. The synapse device stack may implement an AND-type or NOR-type synapse array.