The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2025

Filed:

Apr. 18, 2024
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Yusuke Shima, Yokkaichi, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01); G11C 5/06 (2006.01); H01L 21/3065 (2006.01); H01L 21/3105 (2006.01); H01L 21/67 (2006.01); H01L 21/768 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01); H10D 62/40 (2025.01);
U.S. Cl.
CPC ...
H10B 41/27 (2023.02); G11C 5/025 (2013.01); G11C 5/06 (2013.01); H01L 21/3065 (2013.01); H01L 21/31053 (2013.01); H01L 21/67075 (2013.01); H01L 21/76876 (2013.01); H10B 43/27 (2023.02); H10D 62/40 (2025.01);
Abstract

A semiconductor memory device includes a first region where a plurality of conductive layers, a plurality of insulating layers, a semiconductor layer, and a gate insulating layer are formed and a second region different from the first region above a substrate. The plurality of conductive layers include a plurality of first conductive layers and a plurality of second conductive layers. The semiconductor memory device includes a plurality of first films different from the first conductive layers disposed in same layers as the plurality of first conductive layers in the second region and a plurality of second films different from the second conductive layers and the first films disposed in same layers as the plurality of second conductive layers in the second region.


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