Semiconductor memory device having segmented cell bit line

Abstract

A semiconductor memory device includes: a memory cell array located in a first layer and including a word line, a cell bit line, and a memory cell located in a region where the word line and the cell bit line are crossed; and a bit line sense amplifier located in a second layer, different from the first layer. The bit line sense amplifier is connected to a bit line that is connected to the cell bit line and to a complementary bit line corresponding to the bit line. The bit line sense amplifier detects data stored in the at least one memory cell. Each of the at least one cell bit line is segmented into two or more portions, and the two or more portions are respectively connected to the bit line and the complementary bit line connected to the bit line sense amplifier.