The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 09, 2025
Filed:
Sep. 15, 2023
Huawei Technologies Co., Ltd., Shenzhen, CN;
Zhaohua Qian, Shanghai, CN;
Jingjing Wang, Shenzhen, CN;
Yanqin Chen, Shanghai, CN;
Jiandong Ke, Shanghai, CN;
Huawei Technologies Co., Ltd., Shenzhen, CN;
Abstract
An interface circuit, a method for controlling the interface circuit, a chip, and a terminal device are provided. The interface circuit includes a first PMOS transistor, an input signal control circuit, a bias circuit, a signal input end, and an input/output end. The bias circuit includes a substrate bias voltage generation end and a bias voltage generation end. The bias circuit is coupled to a high-level power supply end, the input/output end, and a ground end. The input signal control circuit is connected to the signal input end, the bias voltage generation end, and a gate of the first PMOS transistor; a first electrode of the first PMOS transistor is connected to the high-level power supply end, and a second electrode of the first PMOS transistor is connected to the input/output end.