The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 09, 2025
Filed:
May. 29, 2024
Epc Power Corporation, Poway, CA (US);
M A Awal, Poway, CA (US);
David Michaud, Poway, CA (US);
EPC Power Corporation, Poway, CA (US);
Abstract
Capacity-optimized grid-forming is provided. A controller includes a power-synchronization model (PSM). The PSM is configured to receive positive and negative sequence symmetrical components of an output voltage and an output current. The PSM is configured to generate current references including a positive and negative sequence current reference. The PSM is configured to generate an internal voltage phase reference and voltage magnitude reference. The controller includes a capacity constrainer to determine, based on the current references and a capacity limit terms, that a device is capacity constrained. The capacity constrainer is configured to determine optimum complex gains to scale the plurality of current references based on the capacity limit terms. The capacity constrainer is configured to, responsive to the determination of constraint, output scaled current reference to cause a power stage to adjust the output voltage/current, the scaled current reference scaled according to the complex gains.