The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2025

Filed:

Jul. 18, 2023
Applicant:

Realtek Semiconductor Corp., Hsinchu, TW;

Inventor:

Cheng-Chen Huang, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5286 (2013.01); H01L 23/5226 (2013.01);
Abstract

A power planning method, a chip device, and a non-transitory computer readable medium for the power planning method are provided. The power planning method is able to be implemented by a circuit that includes a first circuit layer and a second circuit layer. The first circuit layer includes power rails and a first standard circuit unit, and the second circuit layer includes the power rails. The power planning method includes calculating an unused routing area and a used routing area of each of the first circuit layer and the second circuit layer of the circuit; and disposing auxiliary power stripes or auxiliary via pillars to connect the power rails of the first circuit layer and the power rails of the second circuit layer.


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