Memory device including string select transistors having different threshold voltages and method of operating the memory device

Abstract

A memory device including: a memory cell array including a plurality of memory blocks; a voltage generator configured to generate an erase voltage and row line voltages to be provided to a target block of the plurality of memory blocks on which an erase operation is to be performed; and a control logic circuit configured to control the memory cell array and the voltage generator, wherein, during the erase operation, after a precharge voltage is applied to a plurality of string select lines connected to the target block, the control logic circuit is further configured to provide the erase voltage to a plurality of bit lines connected to the plurality of string select lines, wherein the plurality of string select lines includes a first string select line and a second string select line, wherein a first distance between the first string select line and ends of a plurality of word lines connected to the target block is less than a second distance between the second string select line and the ends of the plurality of word lines, and wherein a first threshold voltage of a first transistor connected to the first string select line is higher than a second threshold voltage of a second transistor connected to the second string select line.