The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2025

Filed:

Dec. 20, 2023
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Bo Yang, Santa Clara, CA (US);

Heon C. Kim, Campbell, CA (US);

Vasu P. Ganti, Los Altos, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3185 (2006.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318552 (2013.01); G01R 31/31725 (2013.01); G01R 31/318536 (2013.01); G01R 31/318541 (2013.01); G01R 31/318594 (2013.01);
Abstract

An apparatus includes a first set of scan-enabled flip-flop circuits may be configured to shift a scan-chain pattern from a first test input node to a first test output node using a first clock signal. A particular lockup latch may be coupled to the first test output node and to a second test input node. This particular lockup latch may be configured to, when enabled, delay propagation of the scan-chain pattern from the first test output node to the second test input node. A second set of scan-enabled flip-flop circuits may be configured to shift the scan-chain pattern from the second test input node to a second test output node using a second clock signal, different from the first clock signal. A control circuit may be configured to determine whether to enable the particular lockup latch using a particular scan test signal.


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