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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12490598 B1

PDFFull Text
Date of Patent:
Dec. 02, 2025

Filed:

Dec. 21, 2020

Display device and method of manufacturing same

Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

Yongsun Jo, Paju-si, KR;

Deuksoo Jung, Paju-si, KR;

Woojung Byun, Paju-si, KR;

Juhyuk Kim, Paju-si, KR;

Youngho Kim, Paju-si, KR;

Gunwoo Lee, Paju-si, KR;

Hangyu Jung, Paju-si, KR;

Assignee:

LG Display Co., Ltd., Seoul, KR;

Attorney:

Fenwick & West LLP

Primary Examiner:

Bryan R Junge

Int. Cl.
CPC ...
H10K 59/124 (2023.01); H10K 59/121 (2023.01); H10K 59/123 (2023.01); H10K 59/80 (2023.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10K 59/12 (2023.01); H10K 59/126 (2023.01); H10K 59/38 (2023.01); H10K 71/00 (2023.01);
U.S. Cl.
CPC ...
H10K 59/123 (2023.02); H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/124 (2023.02); H10K 59/80515 (2023.02); H10D 86/481 (2025.01); H10D 86/60 (2025.01); H10K 59/1201 (2023.02); H10K 59/126 (2023.02); H10K 59/38 (2023.02); H10K 59/8792 (2023.02); H10K 71/861 (2023.02);
Abstract

A display device having a bankless structure may comprises: a substrate on which pixels including an emission area and a non-emission area are disposed; a first conductive layer disposed on the substrate, and including a lower electrode of a storage capacitor; an active layer formed on the first conductive layer; a second conductive layer formed on the active layer, and including electrodes of at least one transistor, and an upper electrode of the storage capacitor which is formed in a single pattern with at least one of the electrodes of the at least one transistor; an overcoat layer covering the second conductive layer; and a light-emitting element may be disposed on the overcoat layer, and connected to the upper electrode of the storage capacitor through a via hole, wherein the via hole does not overlap the at least one transistor, when viewed from above.

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