The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Dec. 22, 2023
Applicants:

Zhejiang Jinko Solar Co., Ltd., Zhejiang, CN;

Jinko Solar Co., Ltd., Jiangxi, CN;

Inventors:

Jingsheng Jin, Zhejiang, CN;

Guangming Liao, Zhejiang, CN;

Nannan Yang, Zhejiang, CN;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10F 71/00 (2025.01); H10F 10/14 (2025.01); H10F 10/165 (2025.01); H10F 77/20 (2025.01); H10F 77/30 (2025.01); H10F 77/70 (2025.01);
U.S. Cl.
CPC ...
H10F 77/219 (2025.01); H10F 10/146 (2025.01); H10F 10/165 (2025.01); H10F 71/131 (2025.01); H10F 77/311 (2025.01); H10F 77/315 (2025.01); H10F 77/703 (2025.01); Y02P 70/50 (2015.11);
Abstract

Disclosed are a photovoltaic cell, a method for producing the same and a photovoltaic module. The method includes providing a silicon wafer; forming a tunneling oxide layer on the silicon wafer and a P-type amorphous silicon layer over the tunneling oxide layer; forming N-type dopants on the P-type amorphous silicon layer; performing laser processing on the N-type dopants to cause the P-type amorphous silicon layer to be converted into an amorphous silicon layer having alternatingly arranged P-type amorphous silicon and N-type amorphous silicon; removing the N-type dopant on the amorphous silicon layer and forming a protective layer over the amorphous silicon layer; performing processing on the protective layer and the amorphous silicon layer to form a groove and a protrusion; subjecting the silicon wafer to further processing to increase a depth of the groove; removing the protective layer; and subjecting the silicon wafer to high temperature processing.


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