The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Oct. 24, 2023
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Hajime Kimura, Kanagawa, JP;

Atsushi Umezaki, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); G02F 1/133 (2006.01); G02F 1/1339 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G11C 19/28 (2006.01); H10D 30/67 (2025.01); H10D 84/83 (2025.01); H10D 86/01 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); G02F 1/1333 (2006.01); G02F 1/1343 (2006.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
H10D 86/60 (2025.01); G02F 1/13306 (2013.01); G02F 1/1339 (2013.01); G02F 1/136213 (2013.01); G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); G11C 19/28 (2013.01); H10D 30/6729 (2025.01); H10D 30/673 (2025.01); H10D 30/6755 (2025.01); H10D 30/6757 (2025.01); H10D 84/83 (2025.01); H10D 86/0221 (2025.01); H10D 86/0231 (2025.01); H10D 86/423 (2025.01); H10D 86/441 (2025.01); H10D 86/443 (2025.01); H10D 86/471 (2025.01); H10D 86/481 (2025.01); G02F 1/133302 (2021.01); G02F 1/133345 (2013.01); G02F 1/134309 (2013.01); G02F 2201/121 (2013.01); G02F 2201/123 (2013.01); G09G 3/3677 (2013.01); G09G 2310/0251 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01);
Abstract

A semiconductor device including a circuit which does not easily deteriorate is provided. The semiconductor device includes a first transistor, a second transistor, a first switch, a second switch, and a third switch. A first terminal of the first transistor is connected to a first wiring. A second terminal of the first transistor is connected to a second wiring. A gate and a first terminal of the second transistor are connected to the first wiring. A second terminal of the second transistor is connected to a gate of the first transistor. The first switch is connected between the second wiring and a third wiring. The second switch is connected between the second wiring and the third wiring. The third switch is connected between the gate of the first transistor and the third wiring.


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