The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Jan. 20, 2021
Applicants:

Ordos Yuansheng Optoelectronics Co., Ltd., Inner Mongolia, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Le Gao, Beijing, CN;

Liman Peng, Beijing, CN;

Hongyu Mi, Beijing, CN;

Qianqian Zhang, Beijing, CN;

Xiaofeng Yan, Beijing, CN;

Lingling Ma, Beijing, CN;

Zhiyong Xue, Beijing, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 86/60 (2025.01); G01R 31/28 (2006.01); H10D 86/01 (2025.01); H10D 86/40 (2025.01);
U.S. Cl.
CPC ...
H10D 86/60 (2025.01); G01R 31/2884 (2013.01); H10D 86/021 (2025.01); H10D 86/443 (2025.01);
Abstract

A display substrate includes an underlay substrate, a test signal access pin layer, and a signal access pin layer. The underlay substrate includes a display region and a border region at a periphery of the display region. The border region includes a signal access region at one side of the display region and at least one test signal access region adjacent to the signal access region. The test signal access pin layer is in the at least one test signal access region. The signal access pin layer is in the signal access region. A height difference between a surface of the test signal access pin layer away from the underlay substrate and a surface of the signal access pin layer away from the underlay substrate is greater than 0.


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