The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Dec. 01, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jeonil Lee, Suwon-si, KR;

Gyuhyun Kil, Hwaseong-si, KR;

Doosan Back, Seoul, KR;

Chansic Yoon, Anyang-si, KR;

Junghoon Han, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/01 (2025.01); H10B 12/00 (2023.01); H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 64/27 (2025.01);
U.S. Cl.
CPC ...
H10D 64/021 (2025.01); H10B 12/09 (2023.02); H10B 12/50 (2023.02); H10D 30/0227 (2025.01); H10D 30/601 (2025.01); H10D 64/514 (2025.01); H10B 12/315 (2023.02); H10B 12/34 (2023.02); H10B 12/482 (2023.02);
Abstract

A semiconductor device includes a substrate, a gate dielectric layer on the substrate, the gate dielectric layer including a recess at a side surface thereof, a gate electrode structure on the gate dielectric layer, a gate capping layer on the gate electrode structure, and a spacer structure on the substrate and covering side surfaces of the gate dielectric layer, the gate electrode structure, and the gate capping layer, the spacer structure including a first spacer, a second spacer on the first spacer and covering the recess, and a third spacer on the second spacer, the second spacer and the third spacer including silicon nitride.


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