The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Jan. 19, 2021
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Hans Weber, Bayerisch Gmain, DE;

Björn Fischer, Munich, DE;

Franz Hirler, Isen, DE;

Matteo-Alessandro Kutschak, Ludmannsdorf, AT;

Andreas Riegler, Lichtpold, AT;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/17 (2025.01); H03K 17/687 (2006.01); H10D 30/66 (2025.01); H10D 64/00 (2025.01); H10D 64/27 (2025.01); H10D 84/00 (2025.01);
U.S. Cl.
CPC ...
H10D 62/307 (2025.01); H03K 17/687 (2013.01); H10D 30/668 (2025.01); H10D 64/117 (2025.01); H10D 64/513 (2025.01); H10D 84/143 (2025.01); H10D 84/146 (2025.01);
Abstract

A transistor device is disclosed. The transistor device includes: a semiconductor body (); a drift region () in the semiconductor body (); a plurality of transistor cells (); and a gate node (G) and a source node (S), wherein each of the plurality of transistor cells () includes: a first trench electrode () insulated from the semiconductor body () by a first dielectric layer (); a second trench electrode () insulated from the semiconductor body () by a second dielectric layer (); a source region () and a body region () in a first mesa region () between the first trench electrode () and the second trench electrode (); and a compensation region (), wherein the compensation region () adjoins the body region (), the first dielectric (), the second dielectric (), and forms a pn-junction with the drift region (), and wherein from the first trench electrode () and the second trench electrode () at least the first trench electrode () is connected to the gate node (G).


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