The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Mar. 23, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Giyong Chung, Seoul, KR;

Seungyoon Kim, Seoul, KR;

Jaeryong Sim, Hwaseong-si, KR;

Jeehoon Han, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 41/35 (2023.01); H01L 23/528 (2006.01); H01L 25/065 (2023.01); H10B 41/27 (2023.01); H10B 41/40 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 41/35 (2023.02); H01L 23/5283 (2013.01); H01L 25/0657 (2013.01); H10B 41/27 (2023.02); H10B 41/40 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02);
Abstract

A semiconductor device includes a stack structure and an insulation structure that covers the stack structure, a vertical memory structure that penetrates the stack structure, and a separation structure that penetrates the stack structure and has an upper surface located at a higher level than an upper surface of the vertical memory structure. The stack structure includes three gate stack groups stacked in a vertical direction. Each of the three gate stack groups includes gate layers stacked and spaced apart from each other in the vertical direction. At a height level between a lowermost gate layer and an uppermost gate layer, a side surface of the vertical memory structure includes memory side surface slope changing portions, and a side surface of the separation structure includes separation side surface slope changing portions positioned at substantially a same height level as some of the memory side surface slope changing portions.


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