The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Jun. 15, 2022
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Takeshi Aoki, Ebina Kanagawa, JP;

Masaharu Wada, Yokohama Kanagawa, JP;

Mamoru Ishizaka, Hiratsuka Kanagawa, JP;

Tsuneo Inaba, Kamakura Kanagawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); G11C 11/4091 (2006.01); H10D 30/67 (2025.01);
U.S. Cl.
CPC ...
H10B 12/30 (2023.02); G11C 11/4091 (2013.01); H10B 12/50 (2023.02); H10D 30/6755 (2025.01);
Abstract

A semiconductor memory device comprises a memory cell array. The memory cell array comprises sub arrays. The sub array comprises: memory portions; first semiconductor layers electrically connected to memory portions; first gate electrodes respectively facing first semiconductor layers; a first wiring electrically connected to first semiconductor layers; second wirings connected to first gate electrodes; second semiconductor layers electrically connected to first end portions of second wirings; second gate electrodes facing second semiconductor layers; and a third wiring electrically connected to second semiconductor layers. The memory cell array comprises fourth wirings that extend in one direction across the sub arrays and are connected to second gate electrodes.


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