The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

May. 22, 2023
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Wenyi Song, San Jose, CA (US);

Shadi Barakat, Redwood City, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/408 (2006.01); H03K 3/037 (2006.01); H03K 19/003 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
H03K 19/00361 (2013.01); G11C 11/4082 (2013.01); H03K 3/0375 (2013.01); H03K 19/018521 (2013.01);
Abstract

Driver circuitry for memory controller circuitry includes level shifter circuitry, inverter circuitry, and output circuitry. The level shifter circuitry receives an input data signal and outputs a first level shifted data signal and a second level shifted data signal based on the input data signal. The inverter circuitry is connected to the level shifter circuitry, receives the first level shifted data signal and the second level shifted data signal, and outputs a first inverted data signal via a first output node and a second inverted data signal via a second output node. The inverter circuitry includes mitigation circuitry coupled to the first output node and the second output node and alters one or more of the first inverted data signal and the second inverted data signal. The output circuitry outputs an output data signal based on the first inverted data signal and the second inverted data signal.


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