Single clock delay step in multi-stage switched-capacitor delays

Abstract

A programmable delay device providing a delay resolution of less than 1 ns and a maximum delay of >100 ns over a broad bandwidth is disclosed. The device includes an input stage with M sampling switched capacitor elements, reducing the sampling rate by M. The device includes a programmable delay stage with M programmable switched capacitor banks, each bank having N delay switched capacitor storage elements. The programmable delay stage includes a total of M×N delay switched capacitor storage elements, reducing the sampling rate by M×N. This reduced sampling rate permits smaller sampling switches, with reduced leakage current and longer programmable delay times. The device includes an output reconstruction stage that reconstructs a delayed version of the input signal by combining signals from the programmable delay stage. The sampling clocks for the input and output reconstruction stages are independent, allowing a delay resolution corresponding to the sampling rate.