The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Jul. 26, 2022
Applicant:

Realtek Semiconductor Corp., HsinChu, TW;

Inventors:

Po-Chih Wang, HsinChu, TW;

Hsiao-Tsung Yen, HsinChu, TW;

Ka-Un Chan, HsinChu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03F 3/21 (2006.01); H03F 1/02 (2006.01); H03F 1/56 (2006.01);
U.S. Cl.
CPC ...
H03F 1/0205 (2013.01); H03F 1/565 (2013.01); H03F 3/21 (2013.01); H03F 2200/387 (2013.01);
Abstract

A power amplifying circuit includes a first input terminal applied with a first bias voltage, a first amplifying circuit generating a first output signal and a second output signal according to an input signal and a first matching circuit combining the first output signal and the second output signal to generate an output signal. The first amplifying circuit includes a first transistor having a first electrode coupled to the first input terminal and a second electrode applied with a second bias voltage and a second transistor having a first electrode s coupled to the first input terminal and a second electrode applied with a third bias voltage. The first transistor generates the first output signal according to the first bias voltage and the second bias voltage. The second transistor generates the second output signal according to the first bias voltage and the third bias voltage.


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