The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Nov. 20, 2022
Applicant:

Fuji Electric Co., Ltd., Kawasaki, JP;

Inventor:

Masayoshi Nakazawa, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2023.01); H01L 23/00 (2006.01); H01L 23/053 (2006.01); H01L 23/15 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 23/053 (2013.01); H01L 23/15 (2013.01); H01L 23/5386 (2013.01); H01L 24/48 (2013.01); H01L 2224/48225 (2013.01); H01L 2924/1203 (2013.01); H01L 2924/1206 (2013.01); H01L 2924/13055 (2013.01);
Abstract

A semiconductor module including: a plurality of first semiconductor chips; a resin case provided surrounding an accommodation space for accommodating the plurality of first semiconductor chips; a first gate terminal connected to a gate pad of the plurality of first semiconductor chips; a plurality of first main gate wirings provided in the accommodation space, each of which is connected to the gate pad of the plurality of first semiconductor chips; and a first adjusting gate wiring arranged between at least one of the plurality of first main gate wirings and the first gate terminal, and configured to adjust a difference in wiring lengths between the plurality of first semiconductor chips and the first gate terminal is provided.


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