The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2025
Filed:
Sep. 21, 2022
Applicant:
Kioxia Corporation, Tokyo, JP;
Inventors:
Masayuki Miura, Ota Tokyo, JP;
Kazuma Hasegawa, Kamakura Kanagawa, JP;
Kazushige Kawasaki, Kawasaki Kanagawa, JP;
Assignee:
KIOXIA Corporation, Tokyo, JP;
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 21/563 (2013.01); H01L 24/16 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48149 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73215 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1438 (2013.01); H01L 2924/182 (2013.01);
Abstract
A semiconductor device includes a wiring substrate inside which a wiring layer is provided, a plurality of first semiconductor chips stacked in a shifted manner on the wiring substrate and each provided with a connection terminal on a surface facing the wiring substrate, and a second semiconductor chip having a function different from functions of the first semiconductor chips and provided on the wiring substrate on a side where the connection terminals are electrically connected to the wiring substrate.