The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Sep. 27, 2022
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Sylvester Ankamah-Kusi, Dallas, TX (US);

Yiqi Tang, Allen, TX (US);

Siraj Akhtar, Richardson, TX (US);

Rajen Murugan, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H01L 23/66 (2006.01); H03H 7/01 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/66 (2013.01); H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H03H 7/0115 (2013.01); H03H 7/0138 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 2223/6616 (2013.01); H01L 2223/6644 (2013.01); H01L 2223/6672 (2013.01); H01L 2223/6688 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/142 (2013.01);
Abstract

An electronic device includes a multilevel package substrate, a semiconductor die, and a package structure, the multilevel package substrate having a first level, a second level, and a filter circuit in the first and second levels. The filter circuit includes a filter input terminal, a first capacitor, a first inductor, a second capacitor, a second inductor, a filter output terminal, and a reference terminal. The semiconductor die is attached to the multilevel package substrate and has a conductive structure coupled to one of the terminals of the filter circuit, and the package structure encloses the semiconductor die and a portion of the multilevel package substrate.


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