The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2025
Filed:
Jun. 16, 2022
Semiconductor memory device with wiring layer having defined first, second and passing wiring groups
Kioxia Corporation, Tokyo, JP;
Toru Ozawa, Kamakura, JP;
Yoichi Mizuta, Yokohama, JP;
Kioxia Corporation, Tokyo, JP;
Abstract
A semiconductor substrate includes a first circuit region, a second circuit region, and a third circuit region. A wiring layer includes a first boundary region that includes a first boundary between the first and second circuit regions, a second boundary region that includes a second boundary between the second and the third circuit regions, and a passing wiring region between the first and second boundary regions. The first boundary region includes a first wiring group, the second boundary region includes a second wiring group, and the passing wiring region includes a passing wiring group. The first wiring group, the second wiring group, and the passing wiring group are disposed in a same layer. A wiring disposed in a same layer as the passing wiring group and electrically connected to the second circuit region is included in any one of the first and second wiring groups.