The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2025
Filed:
Jun. 21, 2022
Battelle Memorial Institute, Richland, WA (US);
Jesse T. Holzer, Kennewick, WA (US);
Yonghong Chen, Zionsville, IN (US);
Zhongyu Wu, Carmel, IN (US);
Feng Pan, Sugar Land, TX (US);
Arun Veeramany, Richland, WA (US);
Battelle Memorial Institute, Richland, WA (US);
Abstract
Fast simultaneous feasibility testing (SFT) for management of an electrical power grid is achieved through various innovations. The computation problem relates to evaluation of candidate solutions for external power flows into a power grid, with respect to predetermined constraints and contingencies. A perturbation approach with precomputation is extended to encompass grid states (e.g. time periods) in addition to contingencies. Advantages derive from: fewer factorizations or inversions of large matrices; decoupling of state-dependent and contingency-dependent perturbations, leaving relatively few perturbations jointly dependent on both state and contingency; or making approximations by discarding small jointly dependent terms. Significant computation reductions allow a single workstation to perform SFT for 36 hours of a day-ahead cycle.