The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Dec. 21, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Youngnam Hwang, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06N 3/063 (2023.01); G06N 3/065 (2023.01); G06N 3/08 (2023.01); G11C 11/54 (2006.01); G11C 13/00 (2006.01); G06N 3/045 (2023.01); G11C 7/10 (2006.01); G11C 7/16 (2006.01); H03M 1/12 (2006.01); H03M 1/36 (2006.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06N 3/065 (2023.01); G06N 3/08 (2013.01); G11C 11/54 (2013.01); G11C 13/0002 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/004 (2013.01); G06N 3/045 (2023.01); G11C 7/1006 (2013.01); G11C 7/16 (2013.01); G11C 13/003 (2013.01); G11C 2013/0045 (2013.01); G11C 2013/0054 (2013.01); G11C 2213/79 (2013.01); H03M 1/12 (2013.01); H03M 1/361 (2013.01);
Abstract

A neuromorphic computing device includes a first memory cell array comprising a plurality of resistive memory cells and configured to output a plurality of read currents through a plurality of bit lines or source lines; a second memory cell array comprising a plurality of reference resistive memory cells and configured to output at least one reference current through at least one reference bit line or at least one reference source line; a current-to-voltage converting circuit configured to output a plurality of signal voltages respectively corresponding to the plurality of read currents and output at least one reference voltage corresponding to the at least one reference current; and an analog-to-digital converting circuit configured to convert the plurality of signal voltages to a plurality of digital signals using the at least one reference voltage and output the plurality of digital signals.


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