The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Nov. 28, 2022
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Lin-Ya Yu, San Jose, CA (US);

Alexandre Isoard, San Jose, CA (US);

Hem C. Neema, San Jose, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/323 (2020.01); G06F 30/337 (2020.01); G06F 30/373 (2020.01); G06F 30/398 (2020.01);
U.S. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/323 (2020.01); G06F 30/337 (2020.01); G06F 30/373 (2020.01); G06F 30/398 (2020.01);
Abstract

Implementing burst transfers for predicated accesses in high-level synthesis includes generating, using computer hardware, an intermediate representation of a design specified in a high-level programming language. The design is for an integrated circuit. Using the computer hardware, loop predicate information for one or more conditional statements within a loop body of the intermediate representation is determined. A plurality of memory accesses of the loop body guarded by the one or more conditional statements are determined to be sequential memory accesses based on the predicate information. The intermediate representation is modified by inserting one or more intrinsics therein indicating that the sequential memory accesses are to be implemented using a burst transfer mode of the integrated circuit.


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