The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Jul. 12, 2023
Applicant:

Nanya Technology Corporation, New Taipei, TW;

Inventors:

William Wu Shen, Taipei, TW;

Hao-Huan Hsu, Taoyuan, TW;

Tien Te Huang, New Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/56 (2013.01); G06F 21/55 (2013.01);
U.S. Cl.
CPC ...
G06F 21/566 (2013.01); G06F 21/554 (2013.01); G06F 2221/034 (2013.01);
Abstract

A memory device and a control method of the memory device are provided. The memory device includes a memory array and a control logic circuit. The memory array includes a plurality of memory cell rows. The control logic circuit perform an access on the memory array. The control logic circuit counts a number of the access performed on the memory cell rows to generate a plurality of count values corresponding to the memory cell rows. When a count value corresponding to an accessed memory cell row among the memory cell rows is larger than or equal to a threshold value generated with random number corresponding to the accessed memory cell row, the control logic circuit arranges the memory cell rows nearby the accessed memory cell row into a mitigation operation.


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