Write buffer circuit supporting store release combining of store operations from a memory access stage of a processor instruction pipeline for efficient processing of store release instructions, and related methods

Abstract

Write buffer circuit supporting store release combining of store operations from a memory access stage of a processor instruction pipeline for efficient processing of store release instructions, and related methods. The write buffer circuit is interfaced with an instruction pipeline of a processor to receive and commit (write data) executed store instructions to memory. The write buffer circuit allows launching of store release instructions from a store queue (STQ) to a write combining buffer (WCB) even if pending, older store instructions are not yet committed to non-cacheable memory. The write buffer circuit is configured to delay release of store release instructions from the WCB for their data to be written to non-cacheable memory until any pending, older store instructions have been committed. This facilitates combining of address related store-release instructions in the WCB that can be written to memory in a single write operation.