Method and system for efficient data movement in vector processors

Abstract

The present invention discloses a computer implemented method for efficient data movement operations in vector processors comprising a number of logical registers (), a larger number of physical registers (), and a set of alias counters (), wherein each alias counter () corresponds to a physical register () and stores the number of different logical registers () to which said physical register () is simultaneously assigned. The method of the invention consists of copying the first v, (vector length ()) elements of a source vector from a source logical register () assigned to a source physical register () into a destination vector in a destination logical register () assigned to a destination physical register (). This is done by assigning the source physical register () to the destination logical register (), thus freeing the destination physical register () and by increasing in one unit the alias counter () associated to the source physical register () denoting that said source physical register () is assigned to more than one different logical registers () simultaneously.