The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2025
Filed:
Jan. 08, 2024
Applicant:
SK Hynix Inc., Icheon-si, KR;
Inventor:
Ji Hyo Kang, Icheon-si, KR;
Assignee:
SK hynix Inc., Icheon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/10 (2006.01); G11C 7/22 (2006.01); H03K 3/037 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
G06F 1/10 (2013.01); H03K 3/037 (2013.01); H03K 19/018521 (2013.01); G11C 7/222 (2013.01);
Abstract
A clock distribution network includes an input control circuit and a clock tree. The input control circuit is configured to generate a control input clock signal based on an input clock signal and a low power mode signal. The clock tree is configured to generate an output clock signal by buffering the control input clock signal. When the low power mode signal is enabled, the input control circuit is configured to change a DC level of the control input clock signal.