The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 25, 2025
Filed:
Feb. 14, 2025
Saphlux, Inc., San Diego, CA (US);
Saphlux, Inc., San Diego, CA (US);
Abstract
In some embodiments, methods for fabricating micro-LEDs may include bonding a semiconductor wafer to a Complementary Metal-Oxide-Semiconductor (CMOS) wafer via one or more adhesive layers, etching the LED epilayer and the one or more adhesive layers to form a plurality of micro-LED structures, and fabricating an electrode layer on the plurality of micro-LED structures. The semiconductor wafer may include an LED epilayer including an n-GaN layer, a p-GaN layer, and an active layer positioned between the n-GaN layer and the p-GaN layer. Prior to the bonding of the semiconductor layer to the CMOS wafer, a stress release pattern may be formed in the LED epilayer. The stress release pattern may include a plurality of geometrical shapes (e.g., squares, rectangles, hexagons, rings, etc.) that may facilitate the release of mechanical stresses induced during the subsequent processing of the semiconductor wafer and/or the fabrication of the micro-LEDs.