The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Sep. 08, 2022
Applicant:

Research & Business Foundation Sungkyunkwan University, Suwon-si, KR;

Inventors:

Hae Ju Choi, Suwon-si, KR;

Tae Ho Kang, Seoul, KR;

Chan Woo Kang, Incheon, KR;

Hyeon Je Son, Suwon-si, KR;

Jin Hong Park, Seoul, KR;

Sung Joo Lee, Seongnam-si, KR;

Sung Pyo Baek, Suwon-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 84/85 (2025.01); H02M 7/537 (2006.01); H10D 30/67 (2025.01); H10D 62/13 (2025.01); H10D 88/00 (2025.01); H10D 62/80 (2025.01);
U.S. Cl.
CPC ...
H10D 84/856 (2025.01); H02M 7/537 (2013.01); H10D 30/6729 (2025.01); H10D 30/673 (2025.01); H10D 30/6757 (2025.01); H10D 62/154 (2025.01); H10D 62/158 (2025.01); H10D 88/00 (2025.01); H10D 62/80 (2025.01);
Abstract

A super-steep switching device and an inverter device using the same are disclosed. The super-steep switching device includes a semiconductor channel disposed on a substrate and made of a semiconductor material having impact ionization characteristic; a source electrode and a drain electrode in contact with the semiconductor channel, wherein the source electrode and the drain electrode are disposed on the substrate and are spaced apart from each other; and a gate electrode disposed on the semiconductor channel so as to overlap only a portion of the semiconductor channel, wherein a top surface of the semiconductor channel includes a first area overlapping the gate electrode, and a second area non-overlapping the gate electrode, wherein a ratio of a length of the first area and a length of the second area is in a range of 1:0.1 to 0.4.


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