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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12484285 B1

PDFFull Text
Date of Patent:
Nov. 25, 2025

Filed:

Oct. 05, 2023

Semiconductor device and method for manufacturing the same

Applicant:

Rohm Co., Ltd., Kyoto, JP;

Inventor:

Yuki Nakano, Kyoto, JP;

Assignee:

ROHM CO., LTD., Kyoto, JP;

Attorney:

XSENSUS LLP

Primary Examiner:

Matthew C Landau

Assistant Examiner:

Dmitriy undefined Yemelyanov

Int. Cl.
CPC ...
H10D 64/27 (2025.01); H10D 12/01 (2025.01); H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 30/66 (2025.01); H10D 62/10 (2025.01); H10D 62/17 (2025.01); H10D 62/83 (2025.01); H10D 62/832 (2025.01); H10D 62/85 (2025.01); H10D 64/00 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 64/513 (2025.01); H10D 12/031 (2025.01); H10D 30/01 (2025.01); H10D 30/0297 (2025.01); H10D 30/60 (2025.01); H10D 30/665 (2025.01); H10D 30/668 (2025.01); H10D 62/105 (2025.01); H10D 62/107 (2025.01); H10D 62/8303 (2025.01); H10D 62/8325 (2025.01); H10D 62/8503 (2025.01); H10D 64/025 (2025.01); H10D 64/117 (2025.01); H10D 62/116 (2025.01); H10D 62/127 (2025.01); H10D 62/393 (2025.01);
Abstract

A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.

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