The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Mar. 13, 2023
Applicant:

Borgwarner Us Technologies Llc, Wilmington, DE (US);

Inventors:

Alexandre M. S. Reis, Westfield, IN (US);

Bryan Alan Rohl, Westfield, IN (US);

Thomas Alan Degenkolb, Noblesville, IN (US);

Assignee:

BorgWarner US Technologies LLC, Wilmington, DE (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 7/20 (2006.01); H01L 23/367 (2006.01); H01L 23/40 (2006.01); H01L 25/11 (2006.01);
U.S. Cl.
CPC ...
H05K 7/20445 (2013.01); H01L 23/3675 (2013.01); H05K 7/209 (2013.01); H01L 23/40 (2013.01); H01L 25/115 (2013.01); H01L 2225/06589 (2013.01); H01L 2225/1094 (2013.01); H05K 7/20436 (2013.01);
Abstract

A power semiconductor package includes: a first power semiconductor; a cold plate including a floor and a first pedestal extending from the floor, wherein the first pedestal is configured to support the first power semiconductor; a thermal interface material configured to transfer heat from the first power semiconductor to the first pedestal of the cold plate; and a spacer including: a first frame configured to receive at least a portion of the first pedestal, and a second frame configured to receive the thermal interface material; wherein the spacer is configured to provide a uniform thickness of the thermal interface material between the first pedestal of the cold plate and the first power semiconductor.


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