The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Dec. 08, 2022
Applicant:

Greater Shine Limited, New Taipei, TW;

Inventors:

Su-Lin Low, San Diego, CA (US);

Tianan Tim Ma, San Diego, CA (US);

Hong Kui Yang, San Diego, CA (US);

Hausting Hong, San Diego, CA (US);

Chun-I Lee, San Diego, CA (US);

Jianzhou Li, San Diego, CA (US);

Assignee:

GREATER SHINE LIMITED, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 69/324 (2022.01); H04L 69/18 (2022.01); H04W 80/02 (2009.01);
U.S. Cl.
CPC ...
H04L 69/324 (2013.01); H04L 69/18 (2013.01); H04W 80/02 (2013.01);
Abstract

Methods for providing a layer-2 data stack solution in a data plane and associated devices are provided. In some embodiments, the method includes (i) determining, among a plurality of data stack solutions that are selectable, which layer-2 data stack solution is selected and (ii) causing, according to the selected layer-2 data stack solution, the layer-2 micro controller to intervene with a data plane hardware module that is configured to implement a specific layer-2 data stack function. Each of the plurality of data stack solutions represents a distinctive intervening configuration of a layer-2 micro controller. The layer-2 micro controller is coupled to a number of data plane hardware modules that are configured to implement different layer-2 data stack functions. The intervening configuration of the layer-2 micro controller is indicative of a level of control of the layer-2 micro controller over the data plane hardware modules.


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