Feedback divider in a pll used as a phase/frequency detector

Abstract

A phase-locked loop (PLL) uses a feedback divider to provide phase and frequency information for faster lock. The PLL includes a time to digital converter that generates first phase information indicative of a phase difference between a reference clock and a feedback clock. A digital filter receives the first phase information and generates an oscillator control signal used by an oscillator to generate an oscillator output. A feedback divider uses a ripple counter to divide the oscillator output to generate the feedback clock. One sample of the ripple counter provides second phase information and two samples of the ripple counter provide frequency information, which are used to generate the oscillator control signal. The one sample of the ripple counter is compared to an expected value when the PLL is locked to generate second phase information and a difference between the two samples is used to generate the frequency information.