The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Jul. 28, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Juyoun Choi, Hwaseong-si, KR;

Miyeon Kim, Hwaseong-si, KR;

Jungil Son, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/14 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 24/14 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/14517 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/1205 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/3511 (2013.01);
Abstract

A semiconductor package includes a package base substrate including a potential plate. An interposer is arranged on the package base substrate and comprises at least one interposer through electrode, at least one first connection bump, and at least one second connection bump. A first stacked chip unit is arranged on the interposer and comprises a first semiconductor chip and at least one second semiconductor chips arranged on the first semiconductor chip. At least one passive device unit is arranged on the package base substrate. The at least one passive device unit is spaced apart from the interposer in a horizontal direction parallel to an upper surface of the package base substrate. The at least one first connection bump is a dummy bump. The potential plate electrically connects the at least one first connection bump and a power terminal of the at least one passive device unit to each other.


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