The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Oct. 22, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Brent Anderson, Jericho, VT (US);

Lawrence A. Clevenger, Saratoga Springs, NY (US);

Christopher J. Penny, Saratoga Springs, NY (US);

Nicholas Anthony Lanzillo, Wynantskill, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H10D 86/00 (2025.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); H10D 86/201 (2025.01); H01L 25/0657 (2013.01);
Abstract

A semiconductor structure and method of manufacturing a semiconductor structure having a front side and an opposing backside. An early power delivery network (EBPDN) of wires is built above a substrate layer. Buried power rails (BPRs) are built above levels of the PDN and connected to the EBPDN by short length via connections that can be self-aligned to the back side buried power rails. Both BPRs and vias connections have a common metallization. A front side level of transistor devices are built at the front side of the structure above the BPRs. The resulting formed buried power rail structure has an aspect ratio of height:width greater than 4:1, a height >3 times a height of the formed via structure; and a via structure having a length greater than a height of the formed conductive power rail structure.


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