The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Jan. 26, 2023
Applicant:

Huawei Technologies Co., Ltd., Guangdong, CN;

Inventors:

Fankun Wu, Shanghai, CN;

Yunfei Qiao, Shanghai, CN;

Junhe Wang, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3121 (2013.01); H01L 21/565 (2013.01); H01L 23/293 (2013.01); H01L 23/49811 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/73265 (2013.01);
Abstract

A power module is provided. The power module includes a substrate, and the substrate is used to carry components and pins of the power module. A circuit layer is disposed on the substrate, to complete an electrical connection between the carried components. The components and the pins are disposed on a same surface of the substrate, and the components and the pins are electrically connected by using the substrate. The power module further includes a sealing layer. The sealing layer is sleeved on the pins, the pins are partially exposed on a surface that is of the sealing layer and that faces away from a plastic packaging layer, and a space for accommodating the plastic packaging layer is formed between the sealing layer and the substrate.


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