The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 25, 2025
Filed:
Sep. 09, 2020
Hefei Xinsheng Optoelectronics Technology Co., Ltd., Anhui, CN;
Boe Technology Group Co., Ltd., Beijing, CN;
Yu Ai, Beijing, CN;
Xuewu Xie, Beijing, CN;
Bowen Liu, Beijing, CN;
Yubao Kong, Beijing, CN;
Shi Sun, Beijing, CN;
Hao Liu, Beijing, CN;
Ameng Zhang, Beijing, CN;
Hefei Xiasheng Optoelectronics Technology Co., Ltd., Anhui, CN;
Beijing BOE Technology Development Co., Ltd., Beijing, CN;
Abstract
A method of fabricating an array substrate is provided. The method includes providing a substrate including a gate pad configured to bond a gate driving integrated circuit, a data pad configured to bond a data driving integrated circuit, and a plurality of peripheral layout gate (PLG) proto-lines connecting the gate pad and the data pad; forming a PLG testing pad on the substrate; forming a shorting bar connecting the PLG testing pad to first terminals of the plurality of PLG proto-lines; forming a plurality of testing pins respectively connected to second terminals of the plurality of PLG proto-lines, wherein the plurality of testing pins are formed in a first dummy region of the substrate, the first dummy region is adjacent to an array substrate region of the substrate; and connecting the plurality of testing pins to a probe unit to test connectivity of the plurality of PLG proto-lines.