The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Dec. 31, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Youngin Kim, Incheon, KR;

Jonghyuk Park, Hwaseong-si, KR;

Byoungho Kwon, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); H01L 21/762 (2006.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H01L 21/76229 (2013.01); H10B 12/053 (2023.02); H10B 12/09 (2023.02); H10D 64/027 (2025.01); H10B 12/34 (2023.02); H10B 12/482 (2023.02);
Abstract

A manufacturing method of a semiconductor device includes: etching a substrate, thereby forming a cell trench and a dummy trench; forming a preliminary isolation structure on the substrate, wherein a first dummy recess is formed in the preliminary isolation structure and overlaps with the dummy trench; forming a lower mask layer on the preliminary isolation structure, wherein a second dummy recess is formed in the lower mask layer and overlaps with the first dummy recess; forming a dummy recess filling pattern filling the second dummy recess; forming an upper mask layer on the lower mask layer and the dummy recess filling pattern; forming a gate trench using the lower mask layer and the upper mask layer as a mask; and forming a gate structure in the gate trench.


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