The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Jan. 06, 2024
Applicants:

Stmicroelectronics (Grenoble 2) Sas, Grenoble, FR;

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Antonino Conte, Tremestieri Etneo, IT;

Alin Razafindraibe, Saint Martin d'Hères, FR;

Francesco Tomaiuolo, Acireale, IT;

Thibault Mortier, Grenoble, FR;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0028 (2013.01); G11C 13/0004 (2013.01); G11C 13/003 (2013.01); G11C 2213/79 (2013.01);
Abstract

In an embodiment, a non-volatile memory device is proposed. The device includes a plurality of local pull-up stages distributed along a group of memory portions in a memory array. Each local pull-up stage includes, for each wordline that extends through the group of memory portions, a corresponding local pull-up transistor of an NMOS type. The local pull-up transistors of each local pull-up are configured to locally decouple the corresponding wordline from a node at a first reference potential in response to a wordline that extends through the group of memory portions being selected, and locally couple the corresponding wordline to the node at the first reference potential in response to all the wordlines that extend through the group of memory portions being deselected to restore locally a deselection voltage on a wordline previously selected.


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