The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 25, 2025
Filed:
Oct. 26, 2023
The Trustees of Columbia University IN the City of New York, New York, NY (US);
Mingoo Seok, Tenafly, NJ (US);
Jonghyun Oh, New York, NY (US);
THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK, New York, NY (US);
Abstract
Compute-in-memory (CIM) devices and methods for performing vector-matrix multiplication (VMM) are provided. The disclosed CIM device can include a static random access memory (SRAM) array. The SRAM array can include a plurality of column structures. Each column structure can include eight sub-column structures. Each sub-column structure can include at least one bitcell sharing a pair of a local bitline (LBL) and LBLb that can be connected to a pair of global bitlines (GBL) via switches. Each sub-column comprises at least one NOR gate. An even-numbered bitcell can include a wordline 1 (WL1) for a left access transistors, and an odd-numbered bitcell can include a wordline 2 (WL2) for a right access transistors. Every eight columns (8 columns) can be configured to share a hybrid compressor adder-tree (HCA), followed by a bit-first accumulation (BFA).