The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Aug. 19, 2022
Applicant:

Samsung Display Co., Ltd., Yongin-Si, KR;

Inventors:

Kyungeun Park, Seongnam-si, KR;

Donghyun Hwang, Anyang-si, KR;

Dongkyu Lee, Hwaseong-si, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/20 (2006.01);
U.S. Cl.
CPC ...
G09G 3/20 (2013.01); G09G 2310/027 (2013.01); G09G 2310/0291 (2013.01); G09G 2320/0673 (2013.01); G09G 2330/028 (2013.01);
Abstract

A data driver is disclosed that includes a first digital-to-analog converter, a second digital-to-analog converter, a third digital-to-analog converter, a first pseudo amplifier, a second pseudo amplifier, and a main amplifier. The first digital-to-analog converter includes a first resistor string including first resistors and a first decoder. The second digital-to-analog converter includes a second resistor string including second resistors and a second decoder, and is connected to the first digital-to-analog converter. The third digital-to-analog converter is connected to the second digital-to-analog converter. The first pseudo amplifier includes first and second driving transistors. The second pseudo amplifier includes third and fourth driving transistors. The main amplifier is connected to the first and second pseudo amplifiers, and is configured to generate a reference current. The second resistor string is connected between first and second nodes, and a first output node disposed between the first and second driving transistors is connected to the first node. A second output node disposed between the third and fourth driving transistors is connected to the second node.


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